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| !"# $ %!& ' ( '%)! !' $ ' ! !&* *!!& '!+& '%)! ! &)*! $ , -.- / ,0 !1*! &) )! ! &! & ' &* $ / )) 2 * & ' / & / $!* ,,/0 1 ! ''%)) $ *3 4 5)) 6 43$)) 6 4 ))7 8.#$ a0-a17 ce2 oe we 2048 x 128 x 8 memory array decoder column i/o control circuit gnd vcc i/o data circuit i/o0-i/o7 ce1 ! "# $ # %&'( ! )*$ + $ ) ) , - .)- , - '//0 ) %10 ) 22 )/ // (*)$+-"$+ /)! ) )1"-3 2(',- "- 3 "$4 2(',- 43-53 26-78 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 we ce2 a15 vcc a17 a16 a14 a12 a7 a6 a5 a4 oe a10 ce1 i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3 #5#9 # & /& / / & &&/& ,/& : 5: 9 ;&: && < < ! !! 6 .<; .& 1 2 3 4 5 6 a b c d e f g h a0 a1 ce2 a3 a6 a8 i/o 4 a2 we a4 a7 i/o 0 i/o 5 nc a5 i/o 1 gnd vcc vcc gnd i/o 6 nc a17 i/o 2 i/o 7 oe ce1 a16 a15 i/o 3 a9 a10 a11 a12 a13 a14 ))! 5= >95= $9 3$ & ?5= > = $9 3$ 3 ) '" !.<; ?5$ !!>5$ !!.<; ?5$3>$5 )&@8 ?5> = ')& ? > 5 = 6 6; 5$9 , ! " #! $ ! " $ #! ! % # ! " ! $ "!$! "&" % & ! $ & " $$! % & !! a5 7 && !! a5 7 $ " !! $$! " 0 * '"'1 &&-.- ' a $ a?$5)# $ b && , ' a $ a $)# b 5$ &-.- ' $ >5$3 & , ' ?5$3 5$ & c' .<; ? d# && c' .<; ? d# ' ()*+'$ ", + ! ! "" <! e - e e -'f 061 e e e -'f &&; - - - -'f " - - ; , - e ; 0 * '"'1 #$$ #%& #'&& !!; )! ' a 2$ )$ b 5 b 35 b 5 )# & & a5)#%a% $ b b 3 b & a 2$ )$ b 5$ b 5$ b 5$ )# 0 & 1 a $ b $5 b $5 b $5 / %a5 a 2$%a5 )$ b 3 b 3 b 3 d# &0 & 1 ?5$ $ b 5 b 5 b 5 / 5$ ?5$ 5$ $($ - " ! ! & $. ! -$(+ " ! 0 * '"'1 #$$ #%& #'&& !!; )! ' a 2$ )$ b 5 b 35 b 5 )# & & a5)#%a% $ b b 3 b & a 2$ )$ b 5$ b 5$ b 5$ )# 0 & 1 a $ b $5 b $5 b $5 / %a5 a 2$%a5 )$ b 5 b 5 b 5 d# &0 & 1 ?5$ $ b b b / 5$ ?5$ 5$ $($ - " ! ! & $. ! -$(+ " ! 0 * '"'1 #$$ #%& #'&& " !) b 95 b 55 b # #!! ) b b 95 b 55 &&-) 5 b 5 b b #!! ) b b 95 b 55 / #!! ) b b 95 b 55 #!! ) b 35 b 3 b 5 f && b b b -'f && b 5 5 5 35 f && 5 b 5 b 5 b / f && 5 b 5 b 5 b / f && 5 5 5 5 35 ! $/ - $ !# $/'- ""# $+0' **' " "!$ 1 * , 1 * 2/++ '$ 3 # ++4 &6& * 5$ $ &" 7) & &&)' $ "%! * && 7'& ( ' ( 5 pf including jig and scope output 1 ttl 100 pf including jig and scope output 1 ttl t rc t oha t aa t doe t lzoe t ace1/ t ace2 t lzce1/ t lzce2 t hzoe high-z data valid t hzce address oe ce1 ce2 dout 5 5$ 6 ! * #!! ! - (' 6* (' 7 # " ! ! , 8 6*5 5 data valid t aa t oha t oha t rc d out address 9 #$$ #%& #'&& , !) b 95 b 55 b ,/ b b 5 b / ,/ b b 5 b # &),/ b b 5 b # -%),/ 5 b 5 b 5 b # &) 5 b 5 b 5 b 6& , 5 b b 95 b ;&,/ b 35 b 5 b ;-%),/ 5 b 5 b 5 b ,-'f && b b b 35 -.- f && b b b ! $/ - $ !# $/'- ""# $+0' **' " "!$ 1 * , 1 * 2/++ '$ 3 # ++4 7 , $ % # " $ 8-6*5 5 8 % # 8-% ! !# 8 9 "" 5 $ ! $ $ 8 0 , 5 5 0 * '"' 61 data-in valid data undefined t wc t sce1 t sce2 t aw t ha t pwe (4) t hzwe high-z t lzwe t sa t sd t hd address ce1 ce2 we dout din 0 6 1 : -6*6 ; high-z data undefined data-in valid t wc t sce1 t sa t ha t sce2 t pwe (4) t aw t hzwe t sd t hd t lzwe address din ce1 ce2 we dout , $ % # " $ 8-6*5 5 8 % # 8-% ! !# 8 9 "" 5 $ ! $ $ 8 * <, 5 53= $ (' g + !!%;" ;",*%) $ 3$ ;" & !!a $5 !!?5$ )$0 1 b 5 d# )$0 1 b d# $0 1 b d# $0 1 b 9 d# ;"&) ;",*%) 5 b "!* ) ;",*%) b :6*6 ; v cc t sdr t rdr v dr 0.4v 2.7v ce2 gnd 2.2v data retention mode ce2 0.2v : 6 ; v cc ce1 v cc - 0.2v t sdr t rdr v dr ce gnd 2.7v 2.2v data retention mode 5 !"#$%&%'(!)*+, -.*+ )* ! + ", 4 5)) 6 - 43$)) 6 8 4 ))78.# 95 95 4 5)) 6 95- 43$)) 6 958 4 ))78.# 55 55 4 5)) 6 55- 43$)) 6 558 4 ))78.# '/01,"$%&%'(!)23*+, -+ )* ! + ", 4 5)) 6 - 43$)) 6 8 4 ))78.# 95 95 4 5)) 6 95- 43$)) 6 958 4 ))78.# 55 55 4 5)) 6 55- 43$)) 6 558 4 ))78.# ! "#$ !!! "" " %! % & %'! "( & 4,,5)66777 $#1$ # ,7 |
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